![]() ![]() The proposed design showed superiority when compared with the conventional LFSR and related work in reducing power dissipation and area. ![]() LFSRs are simple to synthesize, meaning that they take relatively few resources and can be run at very high clock rates inside of an FPGA. The proposed 4-bit BS-LFSR achieved an active area of 1241.1588um2 and consumed only 53.8844nW with total power savings of 19.43%. LFSR stands for Linear Feedback Shift Register and it is a design that is useful inside of FPGAs. They compared the results for various parameters like number of. The BS-LFSR was designed in Mentor Graphic – TSMC Design Kit Environment using 130nm complementary metal oxide semiconductor (CMOS) technology. device for implementation is Vertex-4 FPGA board for implementing 8 bit, 16 bit and 32 bit LFSR. The pass transistor merged with transistor stack method yielded a better reduction in power dissipation compared to pass transistor design and NAND gate design. In addition, three different architectures to enhance the feedback element used in BS-LFSR was explored. ![]() To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. About Press Copyright Contact us Creators Advertise Developers Terms Privacy Policy & Safety How YouTube works Test new features NFL Sunday Ticket Press Copyright. In this paper, an enhanced BS-LFSR for low power application is proposed. Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance. ![]()
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